Semiconductor devices equipped with a high-voltage MISFET for use in the area of power electronics require a voltage breakdown performance of about 100V or higher. Various voltage breakdown structures have been proposed. One representative MISFET with a voltage breakdown structure is shown in FIG. 7. In this figure, the numeral 41 represents a p-channel type metal oxide semiconductor field effect transistor MOSFET, the surface of an n.sup.- -type semiconductor substrate 42 with a p.sup.- -type low concentration drain diffusion 43a, a drain region 43 equipped with a p.sup.+ -type high concentration drain diffusion region 43b as an ohmic contact, a p.sup.+ -type source diffusion region 44, and a gate layer 46 formed on a gate oxide film 45. A field oxide film 47 on the surface of the low concentration drain diffusion region 43a has a thickness greater than the gate oxide film 45, and the boundary of the field oxide film 47 with the gate oxide film 45 forms a step. The gate layer 46 extends to directly above the low concentration drain diffusion region 43a beyond this step. This extended part functions as a field plate, thereby raising the voltage between the source and the drain. At the same time, the source diffusion region 44 has an n.sup.+ -type contact region 48 formed on its side, a source electrode 49 being electroconductively connected also to the n.sup.- -type semiconductor substrate 42. These arrangements prevent the occurrence of a latch-up phenomenon. In addition, a drain electrode 50 is electroconductively connected to the high concentration drain diffusion region 43b, and a gate electrode 51 is electroconductively connected to the gate layer 46. If the p-channel MOSFET 41 having this structure has the conductivity type of each part reversed, an n-channel MOSFET 61, as shown in FIG. 8, will result. In this figure, the structure of the n-channel MOSFET 61 is the same as that for the p-channel MOSFET 41, whereas each corresponding part is given the same numeral, and its explanation is omitted.
As described above, the MOSFETs shown in FIGS. 7 and 8 are so structured so that they can resist the breakdown voltage between the source and drain and prevent a latch-up phenomenon. Therefore, a semiconductor device independently constructed using these MOSFETs will exhibit a stable operation. However, because those MOSFETs form MOS sections directly on the semiconductor substrate, the semiconductor device has a problem in that it cannot meet the following requirement. That is, the circuitries have become more complex in recent years as the level of control has been elevated in the area of power electronics. As a result, a great burden has been imposed on system designs. Therefore, there have been attempts to reduce this burden by integrating MOSFETs with different conductivity types and control circuits into one chip. However, as long as the MOS section with a conductivity type corresponding to the substrate conductivity type is formed, it is not possible to form the p-channel MOSFET 41 shown in FIG. 7 and the n-channel MOSFET 61 shown in FIG. 8 on one substrate, so that the above requirement cannot be met, and a device incorporating a push-pull output and a bridge output in one chip cannot be realized.
Accordingly, one concept that eliminates the above problem calls for the adoption of a CMOS structure as in a low voltage MOSFET. However, in the high voltage MOSFET, it is necessary to have a structure that can handle a breakdown voltage at a level not influenced by the operating conditions in the semiconductor region formed on one substrate, as well as a structure that can withstand voltages in the lateral direction. Therefore, an insulation separating structure using embedded layers utilizing an epitaxial film-forming process has been considered but is not practical because of its excessive manufacturing costs. In view of the above problems, the present invention is intended to provide a semiconductor device equipped with both a high-voltage n-channel MISFET and high-voltage p-channel MISFET capable of creating a push-pull circuit in one chip by optimizing the separation structure in addition to adopting a junction separation structure as in the low-voltage MOSFET.